This invention relates generally to computers and more particularly to addressing schemes utilizing segmentation and paging.
U.S. Pat. 4,972,338 issued to Crawford et. al. teaches memory management for a microprocessor system. In the microprocessor architecture an address translation unit is included which provides two levels of cache memory management. Segmentation registers and associated segmentation tables in main memory provide a first level of memory management which includes attributes bits for protection, priority, etc. A second page cache memory and associated page directory and page table and main memory provide a second level of management with independent protection on a page level.
To accommodate newer and/or more advanced architectures, a need exists for an addressing scheme that has a dependent relationship between segmentation and paging.